I lead multidisciplinary engineering teams building AI systems, and I own the architecture that spans them — the mathematics, the compiler and runtime, and the hardware underneath. Ph.D. in signal processing and machine learning, with two decades across artificial intelligence, electronics engineering, mixed-signal IC design, high-performance computing, and deep-learning frameworks. That range is what lets me set direction across hardware, compiler, and ML groups at once: meet each of them in their own language, judge the trade-offs they bring me, and own the interfaces between them so the system converges. As an entrepreneur, I have raised over $3M, led an 11-engineer R&D team through to acquisition, and delivered systems where the silicon, compiler, and model teams all had to agree on one contract.
Skills
Leadership & Architecture: Multidisciplinary team management across hardware, compiler, and ML groups; system architecture ownership and technical roadmap; design review and technical arbitration between specialist teams; end-to-end delivery from architecture through implementation; hiring and mentoring; startup fundraising, partner and customer engagement
AI-Assisted Engineering: Agent-driven development as standard practice — Claude Max / Claude Code agents run across compiler, RTL, firmware, and ML work, from specification and design review through implementation and verification. Experienced at directing and reviewing agent output at the throughput of a small team, and at setting the specification discipline, review gates, and verification practice that make it dependable
Languages: C++, Python, C, CUDA, Verilog/SystemVerilog, Chisel (Scala), RISC-V & custom assembly
Compilers & Runtimes: LLVM backend development (TableGen, instruction selection, register allocation, frame lowering, MC code emission), ISA and ABI design, custom deep-learning framework backends and operators (TensorFlow, PyTorch), code generators, cross-compilation toolchains
Electronics & Silicon: RTL design and verification, FPGA implementation (Xilinx Artix-7, Vivado, timing closure, DSP/LUT budgeting), SoC integration (RISC-V PicoRV32, memory-mapped register banks, DMA, UART), chiplet architecture, mixed-signal integrated-circuit design (Cadence ADE, Spectre, SpectreRF), ASIC portability and pre-tapeout planning
AI/ML: Deep learning, adaptive filtering, model deployment and MLOps, GPU acceleration, numerical precision and fixed-point design (Q-format), Clifford (Geometric) Algebras for neural networks
Performance & Infrastructure: High-performance computing, workload profiling and bottleneck analysis, Linux systems, Docker, Git, CI, cloud infrastructure (AWS, GCP, Azure), NVIDIA platforms
Professional Experience
Founder & CEO - Ogre.run, Tulsa, OK (09/2023 – Present)
Building AI infrastructure for datacenters, from custom compilers and inference systems down to integrated-circuit design. Own the company's technical direction and system architecture across the compiler, RTL, and ML layers.
Chief Architect, Machine Learning (Contract) - Permion.ai, Vienna, VA, USA (Remote) (09/2021 – 12/2023)
Directed the R&D team integrating neurosymbolic AI infrastructure with deep learning models for banking and defense applications. Scaled MLOps for multi-platform deployment and owned the interface between R&D and production engineering.
Founder & Chief Architect - Ogarantia, Paris, France (08/2021 – 03/2024)
Deep-tech consultancy delivering AI solutions to clients in the USA and Europe, with a focus on bringing advanced mathematical frameworks — notably Clifford algebra for neural networks — into production systems.
Co-founder & CTO - Upstride (Acquired by ContentSquare), Paris, France (10/2018 – 07/2021)
Owned the architecture and led the engineering organization behind a geometric-algebra computational engine for deep learning — custom operators and framework backends with GPU acceleration, delivered as a library that model teams could drop into existing training pipelines. Managed a team of 11 engineers spanning mathematics, framework, and systems work, and set the technical roadmap. Raised over $3M, established partnerships with NVIDIA, Google, and AWS, and served clients including BMW. Instrumental in the acquisition by ContentSquare.
Applied Scientist (Machine Learning) - UCit.fr, Paris, France (05/2017 – 09/2018)
Built ML algorithms to optimize HPC systems — predictive models of cluster workload patterns used to improve scheduling and resource utilization. Set UCit's ML R&D strategy.
Postdoctoral Researcher - Thales Group, Palaiseau, France (04/2016 – 02/2017)
Developed adaptive filtering algorithms for real-time data processing at CERN, reducing power consumption in HPC clusters. Supported by the Marie Curie Research Fellowship.
Analog and Mixed-Signal IC Engineer - LSITEC, Sao Paulo, Brazil (02/2009 – 02/2010)
Design, simulation, and verification of analog and digital blocks for application-specific integrated circuits (ASICs), using Cadence tools (ADE, AMS Designer, Spectre, SpectreRF).
Education
Ph.D., Signal Processing and Machine Learning (2012-2016)
University of Sao Paulo (Brazil) & Technical University Munich (Germany)
Thesis: Geometric-Algebra Adaptive Filters
M.Sc., Electronic Systems Engineering (2010-2012)
University of Sao Paulo, Brazil
Specialization in Mixed-Signal Integrated-Circuit Design (2008-2009)
CTI Renato Archer, Campinas, Brazil
B.Sc., Electrical Engineering (2003-2008)
Federal University of Bahia, Brazil
Select Publications
Geometric-Algebra Adaptive Filters – IEEE Transactions on Signal Processing
Geometric-Algebra LMS Adaptive Filter and its Application to Rotation Estimation – IEEE Signal Processing Letters
Clifford Convolutional Neural Networks: Concepts, Implementation, and an Application for Lymphoblast Image Classification - Springer Nature, Advanced Computational Applications of Geometric Algebra
6DOF Point Cloud Alignment using Geometric Algebra-based Adaptive Filtering - IEEE Workshop on Applications of Computer Vision
Professional Affiliations & Honors
Marie Curie Research Fellowship, European Union
IEEE Signal Processing Magazine, Reviewer
NVIDIA Inception Program, Member
Languages
English, Portuguese, French, German
Technical Depth Behind the Architecture (click to expand)
minimalMLAC — an R&D program I direct at Ogre.run covering the full stack for domain-specific AI acceleration: a custom processor, its compiler, an algebra accelerator, and the chiplet framework that hosts them. I set the architecture and built the reference prototypes myself, deliberately — a leader making calls across compiler, RTL, and ML boundaries has to have stood at each of them. The work below is what that fluency is built on. These prototypes were built agent-first — I specify, review, and integrate — the same posture I take with an engineering team.
Custom 16-bit RISC Processor + LLVM Compiler Backend
Architected a 16-bit Harvard-architecture ISA (8 registers, 16 instructions, defined calling convention and ABI) and implemented it in Chisel/SystemVerilog on an Artix-7 FPGA. Specified and prototyped the complete LLVM backend in C++ — target registration, TableGen ISA description, instruction selection, register allocation, frame lowering, MC code emitter and assembly backend (~1,200 lines across 20 source files, building against LLVM 16 and 19+). Built the host-side loader in C and the UART protocol that uploads binaries and returns register state.
Geometric Algebra Hardware Accelerator (Cl(3,0,0))
Took my doctoral mathematics to silicon. A Python generator resolves the algebra's structure once — which blade pairs feed which output, and with what sign — and emits fixed RTL wiring, leaving only multiply-accumulate in hardware. Geometric, inner, and outer products in synthesizable Q16.16 fixed point, verified bit-exact against a C++ reference that matches the gaalet library to machine precision.
Integrated into a self-contained SoC: a PicoRV32 RISC-V core runs C firmware that drives the accelerator over a memory-mapped register bank (operands, opcode, start/done handshake) and self-checks results — the complete "software routine → hardware accelerator → verify" loop.
Chiplet Framework for Domain-Specific Accelerators
Defined the architecture for a modular platform hosting accelerators as chiplets: RISC-V control processor, AXI4-Lite register interface, AXI4-Stream data path, DMA, and the verification and toolchain scaffolding around them. The longer-term goal is a developer testbench that converts software routines into micro hardware accelerators automatically — the generator above is its first working instance.